With the continuous development of display technology, true color LCD displays gradually occupy an important position in embedded display systems with their advantages of high resolution, high contrast, and high definition. At present, there are two main ways to realize LCD display control technology based on embedded platform: ARM embedded LCD controller and independent control device. However, these two implementations have shortcomings. The use of embedded controllers may increase the burden on the processor and limit the display frame rate. The external control devices are not only costly, but also specific and difficult to adapt to different Type of LCD screen.
Based on this problem, here is a design scheme of LCD controller based on ARM and FPGA. On the one hand, this design scheme can increase the writing rate of video memory and reduce the burden on the processor by operating the Framebuffer device under LINUX OS. On the one hand, FPGA is used to realize the design of LCD controller, with short development cycle, low power consumption, and flexible portability, which can be applied to different small and medium-sized LCD screens.
1 System composition and working principle
The system mainly consists of a microcontroller, FPGA (LCD controller), storage unit and peripheral interface. The system block diagram is shown in Figure 1.
Controller design scheme suitable for LCD liquid crystal display
The working process of the system: under the action of the timing control signal generated by the timing generating circuit inside the FPGA, the LCD controller reads the data required for display from the microcontroller through the Framebuffer interface and stores it in the display buffer SRAM. At the same time, the LCD display reads the display data from the display memory SRAM, and directly displays the data information in real time through the data format conversion circuit.
2 System hardware design
2.1 LCD controller
The LCD controller is implemented based on FPGA. This program uses Altera's Cvclone (hurricane) series EPlC6Q240. FPGA has the high-speed data transmission I/O interface, can realize the high-speed display memory reading rate, greatly improve the frame rate of LCD display. At the same time, FPGA is a programmable logic device that can implement complex logic operations and provide complex control timing. The LCD display adopts the LQ035Q3DG01 type TFT-LCD liquid crystal display, the resolution is 320240, and the image signal is in RGB format.
Because SRAM has a higher reading and writing speed, the display cache of this design adopts 1 piece of IS61LV51216AL SRAM, its capacity is 512 KB, and the reading and writing speed is about 10ns. And the size of displaying a frame of image is 125 KB (320x240x2/l024), FPGA reads and writes speed to the display memory is about 200 ns, so meet the system requirement. Figure 2 shows the LCD controller circuit connection diagram.
Controller design scheme suitable for LCD liquid crystal display
2.2 ARM9 microcontroller
The main control unit of this system design adopts ATMEL company AT9lRM9200 (abbreviated as 9200) as MCU, this processor is based on ARM920T kernel, the working frequency is 180 MHz. The performance can reach 200 MI/s, and the system adopts open source LINUX OS. However, ARM9, as the control terminal of the system, needs to complete many tasks such as information collection, processing and external communication, and if the LCD controller also reads data from the memory for display, this will cause the processor to burden, thereby reducing the display cache The rate of reading data affects the real-time display of the LCD. Therefore, an application method based on the Framebuffer interface under LINUX OS is proposed here, which greatly increases the rate of reading data from the display memory, thereby improving the real-time performance of the entire display system. Figure 3 shows the AT91RM9200 interface circuit connection.
Controller design scheme suitable for LCD liquid crystal display
3 System software design
The software design of the system is mainly divided into two parts: LCD controller design based on FPGA and Framebuffer driver design under LINUX OS.
3.1 Design of LCD controller
3.1.1 Composition of LCD controller
The LCD controller of this design scheme is mainly composed of modules such as cache read and write, MCU interface and LCD timing control. The specific composition is shown in Figure 4.
Controller design scheme suitable for LCD liquid crystal display
3.1.2 Design principle of LCD controller
According to the display principle of TFT-LCD liquid crystal screen, the main control signals required for display include pixel clock signal, line/field synchronization signal and enable signal. The resolution of the display screen of this scheme is 320x240, and it is required to design the refresh frequency of the LCD display to be 60 Hz, that is, the field synchronization signal (VSYNC) is 60 Hz. Consists of a line synchronization signal, then the period of a line synchronization signal is 1/(60x240) s, and then the line synchronization signal (HSYNC) is 15 kHz. In the same way, the pixel clock signal (CK) is 5MHz.
The FPGA's built-in phase-locked loop IP module (PLL) is used to divide the FPGA 50 MHz clock signal F_CLK by 10 into a 5 MHz pixel clock signal. Applying the state machine method, using Verilog hardware description language to design the timing control module, it provides the LCD with the control signals VSYNC, HSYNC and ENAB that meet the timing requirements. After the design is completed, the timing simulation is completed under the QuatuslI environment, and the simulation results obtained meet the timing requirements. The simulation diagram is shown in Figure 5.
Controller design scheme suitable for LCD liquid crystal display
SRAM is a video memory module. From Figure 2, it can be seen that the data transmission between the LCD controller and the microcontroller is read in under the clock control of ARM, while the LCD screen is read from SRAM under the control of the pixel clock signal CK. Get data. Aiming at the problem of data transmission between different clock domains, this solution adopts FPGA design to implement asynchronous FIFO to complete.
3.2 Framebuffer drive design
Framebuffer is a driver interface in the Linux kernel, which maps display devices as frame buffers. The platform uses Linux 2. 6.25 kernel. In the Linux 2. 6 kernel, a hierarchical driver design framework is usually used. Hierarchical and classified management of devices, the bottom layer of the driver is the bus driver, and the upper layer is the specific device driver. In the Framebuffer driver, the software design process is as follows: First, register the bus type and apply for system bus resources for the specific device and hardware connection; second, register the specific device driver into the bus link list, and the Linux kernel according to the device driver The provided detection function detects the type of the bus device; finally, the registration of the specific device type is realized in the driver detection function. The following is its specific implementation process.
1) Resource application In the system, the 9200 is connected to the FPGA FIFO interface through the BANK7 of the external bus interface, and the FIFO data is written in the 16-bit static bus mode. According to the driver design framework, the first step of driver design needs to apply for bus resources through the system call platform_device_register function. The code is as follows:
Controller design scheme suitable for LCD liquid crystal display
2) The driver is registered in the specific device driver, by using the module_init macro and module_exit to define the loading and unloading methods of the driver module, and the platform_driver_register function is used in the module registration function to register the platform_driver structure of the specific device into the system bus link list, platform_driver Provide the probe and remove operation methods of specific devices for the bus. The schematic code is as follows:
Controller design scheme suitable for LCD liquid crystal display
Controller design scheme suitable for LCD liquid crystal display
3) Framebuffer device registration In Linux, the framebuffer device information is described through the fb_info structure. In fb_info, the more important structures are fb_var_scree-ninfo, fb_var_screeninfo, and fb_ops. Among them, fb_var_screeninfo records the display controller parameters that can be modified by the user, including screen resolution; fb_fix_screeninfo records the display controller parameters that cannot be modified by the user, such as the physical address of the screen buffer, etc.; fb_ops records the implementation method of specific display device IO operations . The driver registers the display device information recorded by fb_info into the Framebuffer device linked list through the register_-framebuffer function.
In the Linux file system, the major device number of the Framebuffer device is 29, and the minor device number is the frame buffer sequence number. After the Framebuffer device is registered, the Framebuffer device file node is created in the system dev directory through the mknod instruction, and the application layer program can realize the access and operation of the Framebuffer device through the Framebuffer device file.
4 Conclusion
The LCD controller of this design meets the requirements of real-time and display frame rate, displaying at least 25 frames per second. LCD controller technology based on FPGA design has the advantages of wide application, strong portability, short development cycle and low cost, and can be applied to many systems or occasions that require LCD liquid crystal display.
